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CXA3621GE
Fingerprint Sensor
Description The CXA3621GE is an electrostatic capacitance method fingerprint sensor. This monolithic IC integrates the sensor block, sense amplifier (3-bit gain adjustment), sample-andhold, output amplifier and output buffer needed to acquire fingerprint images, as well as the timing generator for determining the operation of these functions onto a single chip. 30 pin LLGA (Plastic)
Features * Electrostatic capacitance type sensor (charge transfer method) * Number of pixels: 192 x 128 * 317 DPI * Low power consumption (50mW or less) When P/S: 18W or less * Single 3.0V power supply * Sensor gain control: 3 bits * S/N ratio improved by on-chip sensor block parasitic capacitance cancel function Applications Fingerprint verification units Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25C) VSS - 0.5 to +7.0 * Supply voltage AVDD, DVDD * Input voltage VI VSS - 0.5 to VDD + 0.5 * Output voltage VO VSS - 0.5 to VDD + 0.5 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -25 to +125 * Allowable power dissipation PD 1100 Recommended Operating Conditions * Supply voltage AVDD, DVDD * Ambient operating temperature Ta
V V V C C mW
2.7 to 3.6 0 to +50
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E02127-PS
CXA3621GE
Block Diagram
C_SP
UC UC
Column Shift Register
C_CLK
UC
........ 128 .........
XSP (D/I)
Timing Generator
SENSOR
128
CLK (D/I)
UC ADCLK (D/O) UC UC UC UC UC ........... 192 ........... UC UC UC UC 192 S_CNT Sense AMP (x192) 192 Load S/H & SW (x192) 192 R_SP Row Shift Register
3bit DAC
3 DI (D/I)
Output Buffer AOUT (A/O)
R_CLK
VOS (Bias)
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CXA3621GE
Detailed Block Diagram
OAMP
BIAS_O
VCS_O
VOS
BUF
Pin Symbol
LAND No. 7C 7D 7E 7F 6B 6C 6D 6E 6F 5B 5C 5D 5E 5F 4F 4E 4D 4C 4B 3F 3E 3D 3C 3B 2F 2E 2D 2C
PAMP_D
PAMP_S
28
SGND (P/S) AVDD (P/S) AVss (P/S) AOUT (A/O) VOS (Bias) VCS_O (Bias) NC DVDD (P/S) DVSS (P/S) CSRO (D/O) RSRO (D/O) C_CK (D/O) ADCLK (D/O) SVDS (D/O) PS (D/I) CLK (D/I) XSP (D/I) DI2 (D/I) DI1 (D/I) DI0 (D/I) TEST3 (D/I) TEST2 (D/I) TEST1 (D/I) VCS_S (Bias) VM (Bias) AVSS (P/S) AVDD (P/S) SGND (P/S)
DC_VOS
27 26
C_CLK
25 C_COUT SR SR[1:128] SVss 128 24 23
C_SP
C_LOG
SVss[1:128] 128
DUMMY SENSOR
DUMMY OUT SAMP
SD1
22 21 20
UC UC UC
........ 128 .........
UC UC UC
S[6:7] S[6:7]N
SVss[1:128]
SR[1:128]
UC
UC
UC
UC
UC
OUT
19 18
SC[1:192]N
SC[1:192]N
UC UC UC ........... 192 (Dummy) ...........
17 16
................ 192................
SENSOR (UC)
192
SAMP (192)
IN_N[1:192]
R_LOG
C_CO
C[1:192]
15 14 13 12
192
SC[1:192]
UC UC UC
192
SC[1:192]
CLK
11 10 9 8
S[3:5]N
VCSN
S[4:5]
SVDD
DCLK
S[3:5]N
S[4:5]
DSR DSVss C_SP
SVDS
XSP
VM
7 6 5 4 3
C_CLK
DCLK SR SD1 SD DI[0:1]
TG
BIAS_SA
DC_VM
2 1
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CXA3621GE
Pin Description Serial No. -- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Land No. 2B 2C 2D 2E 2F 3B 3C 3D 3E 3F 4B 4C 4D 4E 4F 5F 5E 5D 5C 5B 6F 6E 6D 6C 6B 7F 7E 7D 7C Symbol SUB SGND AVDD AVSS VM VCS_S TEST1 TEST2 TEST3 DI0 DI1 DI2 XSP CLK PS SVDS ADCLK C_CK RSRO CSRO DVSS DVDD NC VCS_O VOS AOUT AVSS AVDD SGND I/O Power Power Power Power A/O A/O D/I D/I D/I D/I D/I D/I D/I D/I D/I D/O D/O D/O D/O D/O Power Power -- A/O A/O A/O Power Power Power Description Substrate electrode (chip rear surface electrode) 3.0V (VDD). Sensor lightning conductor electrode. (Connect to the GND which is the other system of operating power supply.) Analog power supply 3.0V. Analog GND. Sense amplifier reference voltage monitor 1.5V (1/2 VDD). (Do not connect.) Sense amplifier current source bias monitor. (Do not connect.) Test mode selection. (Connect to GND.) Test mode selection. (Connect to GND.) Test mode selection. (Connect to GND.) Gain setting input (LSB). Gain setting input. Gain setting input (MSB). Sense start pulse (negative pulse). The column and row shift registers and the timing generator are cleared by this signal. Main clock 2MHz. Power saving mode setting. (Low: Operation; High: Standby) Integrating pulse monitor. (Do not connect.) Delay clock. (Do not connect.) Column shift register clock. (Do not connect.) Column shift register final output. (Do not connect.) Row shift register final output. (Do not connect.) Digital GND. Digital power supply 3.0V. No connection. (Do not connect.) Output amplifier current source bias monitor. (Do not connect.) Output amplifier reference voltage monitor 1.09V (4/11VDD). (Do not connect.) Sensor output. Analog GND. Analog power supply 3.0V. Sensor lightning conductor electrode. (Connect to the GND which is the other system of operating power supply.)
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CXA3621GE
Electrical Characteristics DC Characteristics Item Analog supply voltage Digital supply voltage Current consumption (for operation) Current consumption (for standby) Input voltage (High) Input voltage (Low) Output voltage (High) Output voltage (Low) Input leak current Output voltage Output voltage Symbol AVDD DVDD IDD1 IDD2 VIH VIL VOH VOL IL VM VOS VDD = 3V, P/S = L VDD = 3V, P/S = H, CLK = L Digital (CMOS) input cell Digital (CMOS) input cell VDD = 3V, IOH = -800A VDD = 3V, IOL = 2.4mA VDD = 3V, digital (CMOS) input cell [3V/0V] VDD = 3V VDD = 3V 0.7VDD Vss 2.6 0 -1 1.4 1.00 1.5 1.09 Conditions Min. 2.7 2.7 5.0 (Vss = 0V, Ta = 25C) Typ. 3.0 3.0 8.5 Max. 3.6 3.6 13.0 5 VDD 0.3VDD 3.0 0.4 1 1.6 1.20 Unit V V mA A V V V V A V V
AC Characteristics Item Clock input period Number of sensor defects Output voltage (Air_Level) AOUT 1 2 Output voltage (Water_Level) AOUT Symbol CLK Conditions
(VDD = 3.0V, VSS = 0V, Ta = 25C) Min. 400 0 850 950 1090 1200 3 1350 1450 Typ. Max. Unit ns Defects mV mV
1 Output voltage Air Level means the output level in the condition where nothing is placed against the sensor surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the sensor output and then taking the average. The gain setting for this measurement is (011). 2 Output voltage Water Level specifies the degree to which the output level changes from the Air Level when a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level when a drop of water is placed on the surface) are built into the sensor chip, and the average of these output values is calculated. The difference from the Air Level noted above becomes the Water Level. The gain setting for this measurement is (011).
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CXA3621GE
Electrical Characteristics Measurement Circuit
Digital input pin Digital output pin Analog output pin
AVDD 1.0F AOUT/O VCS_O/O DVDD 0.1F CSRO/O C_CK/O 17 SVDS/O 15 CLK/I 13 DI2/I 11 DI0/I 9 TEST2/I 7 VCS_S/O 5 AVSS SGND 3 1 6 4 2 8 10 12 14 16 18 21 19 22 20 27 25 23 28 26 24
SGND AVSS VOS/O 0.1F NC DVSS RSRO/O ADCLK/O PS/I XSP/I DI1/I TEST3/I TEST1/I VM/O 0.1F AVDD 1.0F
Vcc 3.0V
The load of 30pF or more is added to each pin.
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CXA3621GE
Application Circuit
Microcomputer During registration
Flash Registered data
DRAM During verification ASIC Binary value, verification
Fingerprint sensor chip
8-bit A/D
Verification results
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXA3621GE
Description of Operation * Fingerprint sensor principle The principle of this newly developed fingerprint sensor is described below (Fig. 1). The sensor block contains an array of metal electrodes which are covered on top by an insulating film (overcoat). When a finger (which is conductive matter) is placed directly against this surface, the three elements of the metal electrode, the insulating film and the finger form a capacitor. The difference between the fingerprint ridges and valleys is the difference in distance to the metal electrodes, and becomes the difference in the capacitance values of the individually formed capacitors. (The ridge capacitance values are determined by the dielectric constant of the insulating film, but the valleys contain air in addition to this, making the difference between the ridge and valley capacitance values even greater than the difference in distance.) Using this principle, by applying a constant voltage to all metal electrodes, the charge level accumulated in each electrode differs, making it possible to output the unevenness of the fingerprint as an electric signal by transferring and converting these charges to voltages.
Ridge
Valley
Fingerprint unevenness Overcoat Metal electrode Inter-layer film
Si
Fig. 1
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CXA3621GE
S4 Cf1 Cs Vcel Sensor Array Cp SVss Cp' SVDD VDD Upper: Sensor cell Lower: Dummy block VM S4 Cf1 Vsnsd Vceld Dummy Block Cp SVss Cp' SVDD VDD Sensor block (192 x 128: Sensor cell) (128: Dummy block) VM Sense amplifier block (192: Sensor cell) (1: Dummy block) S3 S_Amp Ch1 Sr Vsld S5 Sd1 S3 S_Amp Ch1 Vsns Sr Vsl S5 Sc
SS Cf2 Ssig Voi Cs1
S6 Cf3 Voo S7
P_Amp VM
O_Amp VOS
Buffer Aout Ch2
SD Cf2 Sdmy
P_Amp VM
Output block (1)
Fig. 2 * Fingerprint sensor operation (Fig. 2) Description of characters Cs: Capacitance formed between the finger and the metal electrode Cp: Parasitic capacitance formed between the metal electrode and the silicon substrate Cp': Capacitance for canceling Cp (Cp Cp') Ch: Hold capacitance Cf: Feedback capacitance for determining the gain S: Switch V: Node voltage VM = 1 VDD, VOS = 4 VDD 2 11
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CXA3621GE
Appearance and Readout Order
15.36mm
Cell (1, 1) 10.24mm Cell (128, 1) Sensor Area 192 x 128
Cell (1, 192)
Scan Formation Cell (1, 1) to Cell (1, 192)
16.8mm Cell (128, 192) Cell (128, 1) to Cell (128, 192)
19.8mm
G
Flip
F
4
9
14
15
20
25
E
3
8
13
16
21
26
D
2
7
12
17
22
27
C
1
6
11
18
23
28
B
5
10
19
24
A 1 2 3 4 5 6 7 8
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CXA3621GE
Notes on Operation Sensor surface electrostatic strength Aerial discharge (150pF, 330): 12kV or more Sony conducts tests using the 50% flash-over method from the viewpoint of reproducibility and comparison of performance. This method allows more stable measurement than the general method of approaching a discharge gun (approach method). However the discharge distance tends to be longer than for the approach method, so the above performances may not be satisfied if testing is performed by the approach method. The discharge distance (distance between the probe tip and the test piece) is determined, and a trigger is applied at fixed time intervals to raise the applied voltage and start discharge. The applied voltage when discharge occurs at just 1/2 of the number of trigger times is the 50% flash-over voltage. The flash-over voltage changes when the distance is changed, but it has been confirmed that there are no problems in terms of sensor performance up to 12kV. Sensor surface strength The sensor surface may be broken by the contact of the metal and others. Therefore, be sure to pay the sufficient attention to handling this IC. Never handle sensors with metal tweezers or similar tools on mounting lines, etc.
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CXA3621GE
Timing Chart
500ns
XSP (3F)
250ns
CLK (4C)
250ns 250ns
Strobe Point
480ns
Input level VIH = 0.7VDD VIL = 0.3VDD
Output level High 0.65VDD X 0.35VDD Low
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CXA3621GE
Input/Output Signal
CLK (Pin 13 * 4E) Input
F = 2MHz
500ns (1CLK) 250ns
XSP (Pin 12 * 4D) Input 750ns 750ns
16512.5s (33025CLK) {(192 + 1 + 63) x (2 + 126) + (192 + 1 + 63) + 1}
(Repeat 128 Times) AOUT (Pin 25 * 7F) Output
1 to 1.2V
256.5s (513CLK) ((192 + 1 + 63) x 2 + 1)
96s (192CLK) 1st line output
32s (64CLK) Sensor read
96s (192CLK) 2nd line output
32s (64CLK) Sensor read
2.3V AOUT (Pin 25 * 7F) Detail 1.1V 500ns (1CLK)
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CXA3621GE
Package Outline
Unit: mm
30PIN LLGA
0.2 SA 20.0
2.6 0.3 0.5 0.3
0.5 0.3 2.42 0.3
19.0 0.25 15.16 0.25 PIN 1 INDEX
1.2 0.1 0.08MAX
10.04 0.25
0.2 S B
16.0 0.25
17.0
(0.4)
1. 0
R
x4 0.15
Y
DETAIL X
SENSOR AREA
4-
3 - 2.2
10.16 A
52 - 1.2 0.08
0.25MAX
0.25MAX
2.3
2.07
0.8
0.1 M S A B
2.54
G F E D C
B
3.42
DETAIL Y
7.1
NOTE : Not include flash burr.
2.07
B A
2.2
1
2
3
4
5
6
78
3.65
2.2 2.3
SONY CODE JEITA CODE JEDEC CODE
2.54
PACKAGE STRUCTURE
PACKAGE MATERIAL ORGANIC SUBSTRATE NICKEL & GOLD PLATING COPPER 0.7g TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS
LLGA-30P-02
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Sony Corporation
0.1 S
X
S
R 0M 1. AX

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